Manufacture testing, characterization and failure analysis of integrated circuits is often complicated and time consuming, especially when circuits are tested at full speed over a range of functional and electrical conditions. While there are unique features associated with each aspect of the testing, there is also considerable overlap both in the testing and in the silicon features that support them. Many existing approaches utilize elaborate external test environments, including a tester. The use of such equipment may increase the cost of manufacturing integrated circuits.
The testing of interface circuits poses additional challenges. During testing, complicated test patterns are often exchanged between the device under test and the tester. Unfortunately, data rates for communication between devices and testers are often lower than the full speed operating data rates of the circuits being tested. As a consequence, test patterns are usually either stored in the device during testing in a memory or buffer, which adds additional expense, or the testing is gated by the communication between the device and the tester. When the test patterns are stored in the device during testing, synchronization of the test results and the corresponding test patterns may be necessary. This is often accomplished by providing external synchronization signals to the device under test. This may further increase the complexity and expense associated with device testing.
There is a need, therefore, for improved approaches for testing and/or characterizing integrated circuits.
Like reference numerals refer to corresponding parts throughout the drawings.